VNA External Clock Modification

Phase-coherent operation (Tier 3) locks all VNAs to a shared 26 MHz reference clock, achieving ±1° phase alignment. This is essential for antenna arrays, MIMO testing, and any measurement where relative phase matters.

Caution

This modification requires PCB surgery—cutting traces and soldering to IC pins. It voids your warranty and risks damaging the VNA if done incorrectly. Only proceed if you’re comfortable with fine-pitch SMD work.

Prerequisites

Complete hardware trigger wiring (Tier 2) first. Phase coherent operation requires both:

1. Shared clock reference (this modification)
2. Hardware trigger synchronization (Tier 2)

When You Need This

Antenna Arrays

Phased arrays require known phase relationships between elements. Software or trigger sync alone can’t provide phase information.

MIMO Systems

Multiple-input-multiple-output antenna characterization needs coherent phase measurement across all paths.

Phase Noise Measurement

Comparing oscillator phase noise requires a more stable reference than the internal crystal.

Beamforming Verification

Verify beam patterns and null depths on multi-element antennas.

Clock Reference Options

Source	Stability	Cost	Best For
OCXO (oven crystal)	~1 ppb	$50-200	Bench work, highest stability
TCXO	~1 ppm	$10-30	Portable, adequate for most
GPS-DO (GPS disciplined)	~0.01 ppb	$100-300	Absolute accuracy, traceable
Single VNA CLK2	Device-dependent	$0	Quick hack, tap one VNA’s Si5351

Tip

For most amateur work, a TCXO is sufficient and much cheaper than an OCXO. The key is that all VNAs share the same reference—absolute stability matters less than matching.

Parts Needed

• 26 MHz reference oscillator (OCXO, TCXO, or GPS-DO module)
• Clock distribution splitter (for 3+ VNAs)
• 100nF DC blocking capacitors (0402 or 0603)
• SMA connectors and coax
• Fine soldering equipment (hot air recommended)

Modification Steps

1. Open the enclosure

   Remove the four screws and carefully separate the front panel from the PCB. Note the ribbon cable to the LCD.

2. Locate the Si5351

   The Si5351 clock generator IC is typically near the MCU. It’s a small QFN package marked “Si5351A” or similar.

   ┌──────────────────────────────────────┐
   │                                      │
   │    ┌─────┐                           │
   │    │Si5351│◄── Clock generator       │
   │    └─────┘                           │
   │       │                              │
   │      [Y1]◄── 26 MHz crystal          │
   │                                      │
   └──────────────────────────────────────┘

3. Cut the crystal trace

   The Si5351 CLKIN pin (pin 1) connects to the on-board 26 MHz crystal. Cut this trace to disconnect the internal crystal:

   • Use a sharp blade or micro drill
   • Cut between the crystal and pin 1
   • Verify with multimeter (no continuity)

   Caution

   This is the point of no return. Once cut, the VNA won’t work without an external clock.

4. Add DC blocking capacitor

   Solder a 100nF capacitor in series with the external clock input:

   External    ┌───┐
   Clock ─────►│100n├────► Si5351 CLKIN (pin 1)
               └───┘

   This blocks any DC offset from your reference source.

5. Add external clock connection

   Options for bringing the clock signal in:

   • SMA connector: Drill the enclosure, mount an SMA
   • Wire: Run a thin coax through an existing opening
   • Test point: Solder to an accessible pad

   Keep the clock path short (< 5cm) to minimize pickup.

6. Reassemble and test

   • Reconnect the LCD ribbon cable
   • Reassemble enclosure
   • Apply external 26 MHz reference
   • Verify VNA powers up and runs

Clock Distribution

For multiple VNAs, distribute the reference clock:

                    ┌──────────────────────┐
                    │  26 MHz Reference    │
                    │  (OCXO or GPS-DO)    │
                    └──────────┬───────────┘
                               │
              ┌────────────────┼────────────────┐
              │                │                │
        ┌─────┴─────┐    ┌─────┴─────┐    ┌─────┴─────┐
        │  VNA #1   │    │  VNA #2   │    │  VNA #N   │
        │ (Leader)  │    │(Follower) │    │(Follower) │
        │           │    │           │    │           │
        │ CLK_IN ←──│────│── CLK ────│────│── CLK     │
        │ TRIG_OUT ─│────│→ TRIG_IN  │    │→ TRIG_IN  │
        └───────────┘    └───────────┘    └───────────┘

Distribution options

Method	VNAs	Notes
Direct	2	Split with 50Ω resistors
Clock buffer IC	2-8	LMK00101, CDCE913, etc.
RF splitter	Any	Power divider, adds insertion loss

Important: Use equal-length cables to all VNAs for matched phase.

Firmware Commands

Custom firmware adds these clock commands:

Command	Description
clk_ref {internal|external}	Select clock source
clk_status	PLL lock status, phase offset

Switching to external clock

raw_command(command="clk_ref external")

The Si5351 PLLs need ~100ms to lock after switching. Check lock status:

raw_command(command="clk_status")
# Output: locked=true, source=external

Using phase_coherent_sweep

Once all VNAs have external clock and trigger wiring:

Say: “Run a phase-coherent sweep on all devices from 430 to 440 MHz”

The assistant calls:

phase_coherent_sweep(
  device_ids=["0001234567", "0009876543", "0005555555"],
  start_hz=430000000,
  stop_hz=440000000,
  points=101
)

This automatically:

1. Switches all devices to external clock
2. Waits for PLL lock (~100ms)
3. Configures trigger (leader + followers)
4. Runs hardware-synced sweep
5. Restores internal clock

Validation

After completing the modification, verify phase coherence:

1. Connect a known reference

   Use a power splitter to feed the same signal to S11 on all VNAs.

2. Measure phase

   Compare S11 phase readings across VNAs at the same frequency. With phase coherence, they should match within ±1°.

3. Sweep and compare

   Run multiple sweeps. Phase should be stable across sweeps—if it drifts, check clock distribution.

Troubleshooting

PLL won’t lock

1. Verify 26 MHz signal at CLKIN (oscilloscope)
2. Check signal level: Si5351 expects 0.6-1.6 Vpp
3. Ensure DC blocking cap is present and not shorted
4. Try different clock source

Phase drifts over time

1. Allow OCXO to warm up (15-30 minutes)
2. Check cable connections for intermittent contact
3. Verify clock splitter isn’t introducing phase shift
4. Avoid temperature changes during measurement

VNA won’t start without external clock

1. Reconnect internal crystal (unsolder cut)
2. Use a backup clock source
3. Consider adding a switch for internal/external

Phase varies with frequency

1. Expected: cables have frequency-dependent phase shift
2. Use matched-length clock distribution cables
3. Calibrate VNAs at each frequency band

Specifications

Parameter	Value
Reference frequency	26 MHz (must match Si5351 XTAL spec)
Input level	0.6-1.6 Vpp into CLKIN
PLL lock time	~100 ms
Phase accuracy	±1° at 1 GHz
Jitter contribution	< 1 ps RMS (typical)

Next Steps

• Multi-VNA Coordination — Understand all three tiers
• Hardware Trigger Wiring — Required for Tier 3
• Tool Reference — Phase coherent tools